Clock gating is a common technique for reducing clock power by shutting off the clock to digital circuit modules by a clock enable signal. A convention approach such as an integrated clock gating cell (ICG) reduces clock power by passing the clock signal only when the ICG is enabled. A conventional ICG uses a clock signal to control the latch, and thus, consumes significant clock switching power. The conventional ICG may use a clock and an inverted clock signal to pass an enable data signal to a latch. Using an inverted clock increases clock power since the ICG is toggling every time the clock switches.